This invention relates to semiconductor integrated circuits and, more particularly, to resistors in those circuits.
It is known that a stress or a strain can cause a resistance charge in a semiconductor material. This property is known as piezoresistance. It has been described in an article by C. S. Smith entitled "Piezoresistance Effect in Germanium and Silicon," Phys. Rev., Vol. 94, No. 1, Apr. 1, 1954, page 42. Throughout this discussion of this invention the terms stress and strain will be used interchangeably.
Advantage has been taken of the piezoresistive effect in stress and strain gauges and transducers. That is, measurements of the resistance change in a semiconductor material have been used to determine the stress or strain applied to that semiconductor material. Stress and strain gauges and transducers are described in, for example, U.S. Pat. No. 3,137,834 issued to W. G. Pfann on June 16, 1964.
Further, it is known to form piezoresistive strain gauges by forming a diffused region of one conductivity type in a semiconductor wafer of the opposite conductivity type. Still further, it is known that it is advantageous to form the region so the direction of current flow in the region is in a sensitive piezoresistive direction. That is, so there is an observable current change resulting from the resistance change due to stress. Such a strain gauge has been described in U.S. Pat. No. 3,266,303 issued to W. G. Pfann on Aug. 16, 1966.
Also, it is known that a problem in the semiconductor art is an imperfect yield during fabrication. In particular, it is known that predictable and proper functioning of circuits sensitive to resistance changes are often difficult to achieve. It would be desirable that the correct values of resistances in a circuit be produced and maintained.
However, it may be sufficient to comply with a less stringent requirement of maintaining the relative values of resistors in a circuit. For example, some linear integrated circuits are designed assuming that relative values rather than absolute values of resistors are maintained. Such circuits can include digital-to-analog converters and voltage regulators. In these cases, elimination of relative resistance changes during fabrication would result in improved yield during fabrication and a cost reduction.
An improvement in integrated circuits can take place by properly appreciating a phenomenon previously thought to be insignificant. Although piezoresistance has been understood, its relationship to the manufacturing process and to an advantageously reliable product has not been completely appreciated. In particular, the effect of piezoresistance on integrated circuits which are not directed toward the measurement of stress and strain has not been fully appreciated. The piezoresistive effect can be of lesser magnitude than such effects as purity of the semiconductor material, crystalline perfection of the semiconductor material, and the number and type of conductivity determining impurities. Typically, these latter effects are carefully taken into account when fabricating semiconductor integrated circuits. It would also be desirable to fully appreciate the significance of piezoresistance on integrated circuits.
Of course, it has been recognized that excessive strain and stress can do damage to an integrated circuit. For example, mechanical weaknesses produced by stresses or strains can result in circuit failure. Accordingly, some attempts have been made at avoiding stresses and strains. However, all significant stresses and strains cannot always be eliminated.
This invention recognizes that remaining stresses and strains can adversely affect production yield and circuit performance. That is, undesirable stressing can occur during packaging a semiconductor chip into a package and during use of the circuit package itself. For example, built-in stresses are produced when impurities are diffused into one side of a semiconductor wafer. Stresses are also produced when a semiconductor wafer is cut into individual chips. When an integrated circuit chip is bonded to a die, the chip can be stressed by mechanical and thermal forces at the interface. The die is usually used to provide mechanical support and a heat sink. A particularly significant effect is the stress induced by the thermal expansion mismatch of a chip and a package during temperature cycling.
A result of such stresses and strains can be improper functioning of the circuit. When a chip is exposed to a nonuniform stress, relative resistance values can be disturbed and hence the circuit behavior can be disturbed too. In addition to recognizing stress produced problems, this invention also provides a means of reducing yield loss when fabricating semiconductor integrated circuits and providing better controlled and more predictable resistance values which, in turn, improve circuit performance.